View K8P3215UQB-PE4B0_3824139.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

flash memory k8p3215uqb revision 1.1 april 2007 1 32mb b-die page nor specification * samsung electronics reserves the right to change products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsu ng products, contact your nearest samsung office. 2. samsung products are not intended for use in life suppor t, critical care, medical, safety equipment, or similar applications where product failure couldresult in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
flash memory k8p3215uqb revision 1.1 april 2007 2 document title 32m bit (2m x16) page mode / multi-bank nor flash memory revision history revision no. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 1.0 1.1 remark target information target information target information target information target information target information preliminary history initial draft -accelerated program time is changed from 4ns to 6ns. -accelerated quad word program time is changed from 1.2ns to 1.5ns. - die version is changed e-die to b-die (k8p3215uqe --> k8p3215uqb) -64fbga 13x11 with 1.0mm ball pitch is added. -56fbga is deleted. -48fbga 6x8.5 is deleted. -56tsop 20x14 is deleted. -cfi code is changed data 00h is changed to 07h in address 35h data 00h is changed to 20h in address 37h -change vih min. from vio-0.4(2.2) to vio-0.4(vccx0.8) -change vil max. from 0.4(0.8) to 0.4(vccx0.2) - group block protect time : 100us --> 120us - group block unprotect time : 1.2ms --> 3ms in figure 8. block group protection & unprotection algorithms & block group protect & unprotect operations timing - package hight is changed from 1.3 0.10 to 1.2 0.10. - 48fbga, 48tsop dimension are added. - specification is finalized. - package ?e? is added in ordering information. - "#oe or #ce should be toggled in each toggle bit status read." is added in dq2 & dq6 toggle bit. draft date october 11, 2006 november 13, 2006 november 21, 2006 january 15, 2007 february 08, 2007 february 15, 2007 march 22, 2007 april 19, 2007 april 23, 2007
flash memory k8p3215uqb revision 1.1 april 2007 3 32m bit (2m x16) page mode / multi-bank nor flash memory ? endurance : 100,000 program/erase cycles minimum ? data retention : 10 years ? vio options at 1.8v and 3v i/o ? package options - 48 pin tsop (20x12mm) - 48 ball fbga (6x8mm, 0.8mm ball pitch) - 64 ball fbga (13x11mm , 1.0 mm ball pitch) the k8p3215uqb featuring single 3.0v power supply, is an 32mbit nor-type flash memory organized as 2mx16. the memory architecture of the dev ice is designed to divide its memory arrays into 78 blocks with independent hardware pro- tection. this block architecture provides highly flexible erase and program capability. the k8 p3215uqb nor flash consists of four banks. this device is capable of reading data from one bank while programming or erasing in the other banks. the k8p3215uqb offers fast page access time of 20~30ns with random access time of 55~70ns. the device s fast access times allow high speed microproces sors to operate without wait states. the device performs a program operation in unit of 16 bits (word) and erases in units of a block. single or multiple blocks can be erased. the block erase operation is completed within typically 0.7 sec. the device requires 17ma as program/ erase current in the commercial and industrial temperature ranges. the k8p3215uqb nor flash memory is created by using samsung's advanced cmos process technology. this device is available in 48 pin tsop package and 48/64 ball fbga pack- age. the device is compatible with eprom applications to require high-density and cost-effective non-volatile read/write storage solutions. features ? single voltage, 2.7v to 3.6v for read and write operations voltage range of 2.7v to 3.1v valid for mcp product ? organization 2m x16 bit (word mode only) ? fast read access time : 55ns ? page mode operation 8 words page access allows fast asychronous read page read access time : 20ns ? read while program/erase operation ? multiple bank architectures (4 banks) bank 0: 4mbit (4kw x 8 and 32kw x 7) bank 1: 12mbit (32kw x 24) bank 2: 12mbit (32kw x 24) bank 3: 4mbit (4kw x 8 and 32kw x 7) ? otp block : extra 256 word - 128word for factory and 128word for customer otp ? power consumption (typical value) - active read current : 45ma (@10mhz) - program/erase current : 17ma - read while program or read while erase current : 35ma - standby mode/auto sleep mode : 15ua ? support single & quad word accelerate program ? wp /acc input pin - allows special protection of two outermost boot blocks at v il , regardless of block protect status - removes special protection of two outermost boot block at v ih, the two blocks return to normal block protect status - accelerated quadword program time : 1.5us ? erase suspend/resume ? program suspend/resume ? unlock bypass program ? hardware reset pin ? command register operation ? block protection / unprotection ? supports common flash memory interface ? operation temperature rnage - industrial temperature : -40 c to 85 c - extended temperature : -25 c to 85 c - commercial temperature : 0 c to 70 c samsung electronics co., ltd. reserves the right to change products and specifications without notice. pin description pin name pin function a0 - a20 address inputs dq0 - dq15 data inputs / outputs ce chip enable oe output enable reset hardware reset pin ry/by ready/busy output we write enable wp /acc hardware write protection/program acceleration vcc power supply v ss ground n.c no connection general description
flash memory k8p3215uqb revision 1.1 april 2007 4 pin configuration 48-pin tsop1 standard type 12mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a1 a15 a4 a14 a2 a3 a8 a9 a10 a12 a16 n.c vss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq9 dq1 dq8 dq0 oe vss ce a0 a11 a13 a19 a20 reset n.c wp /acc ry/by we a17 a7 a18 a6 a5 dq2
flash memory k8p3215uqb revision 1.1 april 2007 5 1 2 3 4 5 6 a b c d e f 7 8 h g nc nc a19 dq5 nc nc nc vss nc nc a12 a14 a15 a16 nc dq15 a13 vss a8 a10 a11 dq7 dq14 dq13 a9 dq6 reset nc dq12 vcc we dq4 wp /acc a18 dq10 dq11 ry/by dq3 a17 a6 a5 dq0 dq8 dq9 a7 dq1 a4 a2 a1 a0 ce oe a3 vss nc nc nc nc nc nc nc nc 64 ball fbga top view (ball down) a20 dq2
flash memory k8p3215uqb revision 1.1 april 2007 6 interface & bank control x dec y dec latch & control latch & control dec x y dec erase control program control high voltage gen. bank 1 cell array bank 0 address bank 1 address bank 0 cell array x dec y dec latch & control bank 3 cell array block inform bank 3 address i/o vcc vss ce oe we reset ry/by a0~a20 dq0~dq15 wp /acc a7 we a13 a17 reset a12 a6 a18 n.c a14 a5 a20 a15 dq2 dq8 dq9 dq3 dq10 dq11 dq4 dq12 vcc dq6 dq14 dq13 a16 vss rfu dq15 dq1 a b c d e f g h 12 345 6 a4 a2 a1 a0 oe a8 a10 a3 ry/ by a9 wp / acc a19 a11 dq5 dq7 ce dq0 vss 48 ball fbga top view (ball down) functional block diagram
flash memory k8p3215uqb revision 1.1 april 2007 7 table 1. product line-up notes : 1. o nly 4c or 4d speed options can be prov ided in case of using 1.65~1.95v v io . speed item speed option 4a 4b 4c 4d vcc 2.7v~3.6v vio (1) 1.65~1.95v , 2.7~3.6v max. address access time (ns) 55ns 60ns 65ns 70ns max. ce access time (ns) 55ns 60ns 65ns 70ns max. oe access time (ns) 20ns 25ns 25ns 30ns max. page access time (ns) 20ns 25ns 25ns 30ns ordering information k8 p 32 15 u q b - p e 4 a samsung nor flash memory device type page mode density & bank architecture 32 mbits & 4 banks operating temperature range c = commercial temp. (0 c to 70 c) i = industrial temp. (-40 c to 85 c) e = extended temp. (-25 c to 85 c) block architecture q = top and bottom boot block version 3th generation access time 4a = 55ns/20ns 4b = 60ns/25ns 4c = 65ns/25ns 4d = 70ns/30ns operating voltage range 2.7v to 3.6v package p = tsop1(lead free), d = fbga(lead free) e = fbga(lead free, 1.0mm ball pitch) organization x16 table 2. k8p3215uqb device bank divisions bank 0, bank 3 bank 1, bank 2 mbit block sizes mbit block sizes 4 mbit 4 kw x 8 and 32 kw x 7 12 mbit 32 kw x 24 table 3. otp block after entering otp block, any issued addresses should be in the range of otp block address otp block address a20~a8 area block size address range 0000h factory-locked area 128 words 000000h-00007fh customer-locked area 128 words 000080h-0000ffh
flash memory k8p3215uqb revision 1.1 april 2007 8 table 4. k8p3215uqb device bank divisions bank number of blocks block size 0 84 kwords 7 32 kwords 1 24 32 kwords 2 24 32 kwords 3 7 32 kwords 84 kwords
flash memory k8p3215uqb revision 1.1 april 2007 9 product introduction the k8p3215uqb is an 32mbit nor-type flash memory. the device features single voltage power supply operating within the range of 2.7v to 3.6v. the device is programmed by using the channel hot electron (che) inject ion mechanism which is used to program eproms. the device is erased elec trically by using fowler-n ordheim tunneling mechanism. to provide highly flexible erase and program capability, the device adapts a block memory architecture that divides its memory array into 78 blocks (4 kw x 16 , 32 kw x 62). programming is done in units of 16 bits (word). all bits of data in one or multiple blocks can be erased simulta neously when the device executes the erase operation. to prevent the devic e from accidental erasing or ov er-writing the programmed data , 78 memory blocks can be hardware protec ted. the device offers fast page access time of 20~30ns with random access time of 55~70ns supporting high speed microprocessors to operate without any wait states. the command set of k8p3215uqb is fully compatible with stan dard flash devices. the device is controlled by chip enable (ce ), out- put enable (oe ) and write enable (we ). device operations are executed by sele ctive command codes. the command codes to be combined with addresses and data are sequentially written to the command registers using microproc essor write timing. the com- mand codes serve as inputs to an internal state machine which c ontrols the program/erase circuitr y. register contents also inte rnally latch addresses and data necessary to execute the program and eras e operations. the k8p3215uqb is implemented with internal program/erase algorithms to execute the program/erase operations . the internal program/erase algorithms are invoked by pro- gram/erase command sequences. the internal program algorithm aut omatically programs and verifies data at specified addresses. the internal erase algorithm automatically pre-programs the me mory cell which is not progra mmed and then executes the erase operation. the k8p3215uqb has means to indicate the status of completion of program/erase operations. the status can be indi- cated via the ry/by pin, data polling of dq7, or the toggle bit (dq6). once the operations have been completed, the device auto- matically resets itself to the read mode. table 5. operations table operation ce oe we wp / acc a9 a6 a1 a0 dq8/ dq15 dq0/ dq7 reset read l l h l/h a9 a6 a1 a0 d out d out h stand-by h x x (2) x x x x high-z high-z (2) output disable l h h l/h x x x x high-z high-z h reset x x x l/h x x x x high-z high-z l write l h l (4) a9 a6 a1 a0 d in d in h enable block protect (3) l h l l/h x l h l x d in v id enable block unprotect (3) l h l (4) x h h l x d in v id temporary block unprotect x x x (4) x x x x x x v id auto select manufacturer id (5) llhl/hv id lll x code (see ta b l e 7 ) h auto select device code (5) llhl/hv id llh x code (see ta b l e 7 ) h notes : 1. l = v il (low), h = v ih (high), v id = 8.5v to 9.5v, d in = data in, d out = data out, x = don't care. 2. wp /acc and reset pin are asserted at vcc 0.2 v or vss 0.2 v in the stand-by mode. 3. addresses must be composed of the block address (a12 - a20). the block protect and unprotect operations may be implemented via programming equipment too. refer to the "block protection and unprotection". 4. if wp /acc = v il, the two outermost boot blocks is protected. if wp /acc = v ih, the two outermost boot block protection depends on whether those blocks were last protected or unprotected using the method described in "block protection and unprotection". if wp /acc = v hh , all blocks will be temporarily unprotected. 5. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 7.
flash memory k8p3215uqb revision 1.1 april 2007 10 table 6. command sequences command sequence cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle read addr 1 r a data rd reset addr 1 xxxh data f0h autoselect manufacturer id (1,2) add 4 555h 2aah da/555h da/x00h data aah 55h 90h ech autoselect device code (1,2,3) addr 4 555h 2aah da/555h da/x01h da/x0eh da/x0fh data aah 55h 90h 257eh 2503h 2501h autoselect b l o c k p r o t e c t v e r i f y ( 1 , 2 ) addr 4 555h 2aah da/555h ba / x02h data aah 55h 90h (see table 7) autoselect otp factory protect addr 4 555h 2aah da/555h x03h data aah 55h 90h (see note 10) program addr 4 555h 2aah 555h pa data aah 55h a0h pd unlock bypass addr 3 555h 2aah 555h data aah 55h 20h unlock bypass program addr 2 xxxh pa data a0h pd unlock bypass block erase addr 2 xxxh ba data 80h 30h unlock bypass chip erase addr 2 xxxh xxxh data 80h 10h unlock bypass reset addr 2 xxxh xxxh data 90h 00h unlock bypass cfi addr 1 xxh data 98h chip erase addr 6 555h 2aah 555h 555h 2aah 555h data aah 55h 80h aah 55h 10h block erase addr 6 555h 2aah 555h 555h 2aah ba data aah 55h 80h aah 55h 30h block erase suspend (4, 5) addr 1 da data b0h block erase resume addr 1 da data 30h program suspend (6,7) addr 1 da data b0h program resume addr 1 da data 30h cfi query (8) addr 1 55h data 98h command definitions the k8p3215uqb operates by selecting and executing its operat ional modes. each operational mode has its own command set. in order to select a certain mode, a proper command with specific address and data sequences must be written into the command reg- ister. writing incorrect information whic h include address and data or writing an impr oper command will reset the device to the read mode. the defined valid register command s equences are stated in table 6. note that erase suspend (b0h) and erase resume (30h) commands are valid only while the bl ock erase operation is in progress. program suspend (b0h) and program resume (30h) commands are valid during program operation and erase sus pend - program operation. only read operation is available after program suspend operation.
flash memory k8p3215uqb revision 1.1 april 2007 11 table 6. command sequences (continued) command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle accelerated program addr 2 xxh pa data a0h pd quadruple word accelerated program(9) addr 5 xxxh pa1 pa2 pa3 pa4 data a5h pd1 pd2 pd3 pd4 enter otp block region addr 3 555h 2aah 555h data aah 55h 88h exit otp block region addr 4 555h 2aah 555h xxx data aah 55h 90h 00h otp protection bit program (11,12) addr 6 555h 2aah 555h ow ow ow data aah 55h 60h 68h 48h rd(0) otp protection bit status addr 5 555h 2aah 555h ow ow data aah 55h 60h 48h rd(0) notes : ? ra : read address, pa : program address, rd : read data, pd : program data ? da : bank address (a19- a20), ba : block address (a12 - a20), abp : address of the block to be protected or unprotected, x = don?t care . ? ow = address (a7:a0) is (00011010), rd(0) = read data dq0 for protection indicator bit ,rd(1) = read data dq1 for ppb lock st atus. ? dq8 - dq15 are don?t care in command sequence, except for rd and pd. ? a11 - a20 are also don?t care, except for the case of special notice. 1. to terminate the autoselect mode, it is necessary to write reset command to the register. 2. the 4th cycle data of autoselect mode is output data. the 3rd and 4th cycle bank addresses of autoselect mode must be same. 3. device id must be read across cycles 4, 5 and 6. k8p2815u(xoeh = 2508h, x0fh = 2501h) , k8p6415u(xoeh = 2506h, x0fh = 2501h), k8p3215u(xoeh = 2503h, x0fh = 25 01h) 4. the read / program operations at non-er asing blocks and the autoselect mode are allowed in the erase suspend mode. 5. the erase suspend co mmand is applicable only to the block erase operation. 6. the read operation is allowed in the program suspend mode. 7. the program suspend command is applicable to program and erase suspend - program operation. 8. command is valid when the device is in read mode or autoselect mode. 9. quadruple word accelerated program is invoked only at vpp=vid, vpp setup is required prior to this command se quence. pa1,pa2,pa3,pa4 have the same a20~a2 address 10. the data is dq6=1 for customer locked and dq7=1 for factory locked. 11. reset command returns device to reading array. 12. cycle 4 programs the addressed locking bit. cycle 5 and 6 validate bit has been fully programmed when dq0=1. if dq0=0 in cycle 6, program command must be issued and verified again. notes : 1. l=logic low=v il , h=logic high=v ih , da= bank address, ba=block address, x=don?t care . description ce oe we a20 to a12 a10 a9 a8 a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq8 dq7 to dq0 manufacturer id l l h da x v id xl l x llll x ech devi ce id read cycle 1 llhdaxv id xl l l l l l h 25h 7eh read cycle 2 h h h l 25h 03h read cycle 3 h h h h 25h 01h block protection veri- fication llhbaxv id xl l l llhl x 0 1 h ( p r o e c t e d ) 00h (unproteced) otp indicator bit (dq7. dq6) llhdaxv id xxl l l lhh x d q 7 = 1 ( f a c t o r y l o c k e d ) dq6=1(customer locked) master locking bit indicator bit llhbaxv id xl l l lhhh x 0 1 h ( p r o e c t e d ) 00h (unproteced) table 7. k8p3215uqb autoselect codes , (high voltage method)
flash memory k8p3215uqb revision 1.1 april 2007 12 device operation read mode the k8p3215uqb is controlled by chip enable (ce ), output enable (oe ) and write enable (we ). when ce and oe are low and we is high, the data stored at the specified address location,wi ll be the output of the device. the outputs are in high impedance state whenever ce or oe is high. the k8p3215uqb is avail able for page mode. page mode provides fast access time for high perfor- mance system. standby mode the k8p3215uqb features stand-by mode to reduce power consum ption. this mode puts the device on hold when the device is deselected by making ce high (ce = v ih ). refer to the dc characteristics for more details on stand-by modes. output disable the device outputs are disabled when oe is high (oe = v ih ). the output pins are in high impedance state. automatic sleep mode the k8p3215uqb features automatic sleep mode to minimize t he device power consumption. when addresses remain steady for t aa +30ns, the device automatically activates t he automatic sleep mode. in the sleep mode, output data is latched and always avail- able to the system. when addresses are changed, the device provides new data without wait time. data outputs t aa + 30ns data auto sleep mode address data data data data figure 1. auto sleep mode operation autoselect mode the k8p3215uqb offers the autoselect mode to identify manufactu rer, device type and block protec tion verification by reading a binary code. the autoselect mode allows programming equipment to automatically match the device to be programmed with its cor- responding programming algorithm. in addition, this mode allows th e verification of the status of write protected blocks. this mode is used by two method. the one is high voltage method to be required v id (8.5v - 9.5v) on address pin a9. when a9 is held at v id and the bank address or block address is asserted, the device outputs the valid data via dq pins(see table 7 and figure 2). the res t of addresses except a0, a1 and a6 are don t care. the other is autoselect command met hod that the autoselect code is accessable by the commamd sequence without v id. the manufacturer, device code and block protec tion verification can be read via the command register. the command sequence is shown in table 7 and figure 3. the autoselect operation of block protection verification is i niti- ated by first writing two unlock cycle. t he third cycle must contain the bank addre ss and autoselect command (90h). if block ad dress while (a6, a1, a0) = (0,1,0) is finally asserted on the address pin, it will produce a logical "1" at the device output dq0 to indicate a write protected block or a logi cal "0" at the device output dq0 to indicate a write unprotected block. to terminate the autose lect oper- ation, write reset command (f0h) into the command register.
flash memory k8p3215uqb revision 1.1 april 2007 13 figure 3. autoselect operation ( by command sequence method ) write (program/erase) mode the k8p3215uqb executes its program/erase operations by writing commands into the command register. in order to write the com- mands to the register, ce and we must be low and oe must be high. addresses are latched on the falling edge of ce or we (which- ever occurs last) and the data are latched on the rising edge of ce or we (whichever occurs firs t). the device uses standard microprocessor write timing. program the k8p3215uqb can be programmed in units of a word. programming is writing 0's into the memory array by executing the internal program routine. in order to perform the internal program ro utine, a four-cycle command seque nce is necessary. the first two cycles are unlock cycles. the th ird cycle is assigned for the program setup command. in the last cycle, the address of the memo ry location and the data to be programmed at that location are wr itten. the device automatically generates adequate program pulses and verifies the programmed cell margin by the internal program routine. during the execution of the routine, the system is not required to provide further controls or timings. during the internal program routine, commands written to the dev ice will be ignored. note that a hardware reset during a progra m operation will cause data corrupti on at the corresponding location. figure 4. program command sequence we 555h 2aah 555h aah 55h a0h program program program start dq15-dq0 address data ry/by figure 2. autoselect operation ( by high voltage method ) note : the addresses other than a0 , a1 and a6 are don t care. please refer to table 7 for device code. note : the 3rd cycle and 4th cycle address must include the same bank address. please refer to table 7 for device code. address a9 v id 00h 01h ech manufacturer id a6,a1,a0* dq15-dq0 return to read mode v = v ih or v il device id ( k8p3215uqb ) 257eh 0eh 2503h 0fh 2501h we 555h 2aah 555h aah 55h 90h 00h 01h ech manufacturer id device id address dq15 dq0 ( k8p3215uqb ) 257eh 0eh 2503h 0fh 2501h
flash memory k8p3215uqb revision 1.1 april 2007 14 in accross block boundaries and any sequence programming is allowed. a bit cannot be programmed from ?0? back to ?1?. if attemp t- ing to do, it may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful . however, a succeeding read will show that the data is stil l ?0?. only erase operations can convert a ?0? to a ?1?. unlock bypass the k8p3215uqb provides the unloc k bypass mode to save its operation time. this mode is possible for program, block erase and chip erase operation. there are two methods to enter the unloc k bypass mode. the mode is invoked by the unlock bypass command sequence. unlike the standard program/erase command sequence that contains four to six bus cycles, the unlock bypass program/ erase command sequence comprises only two bus cycles. the unlock bypass mode is engaged by issuing the unlock bypass com- mand sequence which is comprised of three bus cycles. writing first two unlock cycles is followed by a third cycle containing t he unlock bypass command (20h). once the device is in the un lock bypass mode, the unlock bypass program/erase command sequence is necessary. the unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (a0h) is followed by the program addr ess and data. this command sequence is the only valid one for programming the device in the unlock bypass mode. also, the unlock bypass erase command seque nce is comprised of two bus cycles; writing the unlock bypass block erase command(80h-30h) or writing the unlock bypass chip erase command(80h-10h). this command sequences are the only valid ones for erasing the devic e in the unlock bypass mode. the unlock bypass reset command sequence is the only valid command sequence to exit the unloc k bypass mode. the unlock bypass reset command sequence con- sists of two bus cycles. the first cycle must contain the data ( 90h). the second cycle contains only the data (00h). then, the device returns to the read mode. chip erase to erase a chip is to write 1 s into the entire memory array by executing the in ternal erase routine. the chip erase requires six bus cycles to write the command sequence. the erase set-up command is written after first two "unlock" cycles. then, there are two more write cycles prior to writing the chip erase command. the internal erase routine automatic ally pre-programs and verifies t he entire memory for an all zero data pattern prior to erasi ng. the automatic erase begins on the rising edge of the last we or ce pulse in the command sequence and terminates when dq7 is "1". after that the device returns to the read mode. figure 5. chip erase command sequence we 555h 2aah 555h aah 55h 80h 555h chip erase start dq15-dq0 2aah aah 55h 10h ry/by 555h block erase to erase a block is to write 1 s into the desired memory block by executing the in ternal erase routine. the block erase requires six bus cycles to write the command sequence shown in table 6. afte r the first two "unlock" cycles, the erase setup command (80h) i s written at the third cycle. then there ar e two more "unlock" cycles followed by the block erase command. the internal erase rou tine automatically pre-programs and verifies the entire memory prio r to erasing it. the block addres s is latched on the falling edge of we or ce , while the block erase command is latched on the rising edge of we or ce . multiple blocks can be erased sequentially by writing the six bus-cycle operation in figure 6. upon completion of the last cycl e for the block erase, additional block addr ess and the block erase command (30h) can be writte n to perform the multi-block erase. an 50u s (typical) "time window" is required between the block erase command writes. the block erase command must be written within the 50us "time window", otherwise the block erase command will be ig nored. the 50us "time window" is reset when the falling edge of the we occurs within the 50us of "time window" to latch the bloc k erase command. during the 50us of "time window", any command other than the block erase or the erase suspend command written to the device will reset the dev ice to read mode. after the 50 us of "time window", the block erase command will initiate the inte rnal erase routine to erase the selected blocks. any block eras e address and command following the exceeded "time window" may or may not be accepted. no other commands will be recognized except the erase suspend command. address
flash memory k8p3215uqb revision 1.1 april 2007 15 we dq15-dq0 figure 7. erase suspend/resume command sequence erase suspend / resume the erase suspend command interrupts the block erase to read or program data in a block that is not being erased. the erase sus - pend command is only valid during the block erase operation including the time window of 50us. the erase suspend command is not valid while the chip erase or the in ternal program routine sequence is running. when the erase suspend command is written during a block eras e operation, the device requires a maximum of 20us to suspend the erase operation. but, when the erase suspend command is writt en during the block erase time window (50us) , the device imme - diately terminates the block erase time window and suspends the erase operation. after the erase operation has been suspended, the device is availble for reading or programming data in a block that is not bei ng erased. the system may also write the autoselect comm and sequence when the device is in the erase suspend mode. when the erase resume command is executed, the block erase oper ation will resume. when the erase suspend or erase resume command is executed, the addresses are in don't care state. figure 6. block erase command sequence address 555h block address aah 30h xxxh erase resume xxxh b0h 30h erase suspend block erase start block erase command sequence program suspend / resume the program suspend command interrupts the program operation. also the program suspend command interrupts the program operation during erase suspend mode. the read operation is av ailable only during program sus pend. when the program suspend command is written during a program operation, the device requi res a maximum of 10us to suspend the program operation. the system may also write the autoselect command sequence when the device is in the program suspend mode. when the program resume command is executed, the program operation will resu me. when the program suspend or program resume command is executed, the addresses are in don't care state. we 555h 2aah 555h aah 55h 80h 555h block erase start dq15-dq0 2aah block address aah 55h 30h ry/by address
flash memory k8p3215uqb revision 1.1 april 2007 16 read while write the k8p3215uqb provides multi-bank memory architecture that di vides the memory array into four banks. the device is capable of reading data from one bank and writing data to the other bank simu ltaneously. this is so called the read while write operation with multi-bank architecture; this feature provides the capability of executing the read operation du ring program/erase or erase-sus pend- program operation. the read while write operation is prohibited du ring the chip erase operation. it is also allowed during eras e operation when either single block or mu ltiple blocks from same bank are loaded to be erased. it means that the read while writ e operation is prohibited when blo cks from one bank and another blocks from the other bank are loaded all together for the multi- block erase operation. write protect (wp ) the wp /acc pin has two useful functions. the one is that certain boot block is protecte d by the hardware method not to use v id . the other is that program operation is accelerated to reduce the program time (refer to accelerated program operation paragraph ). when the wp /acc pin is asserted at v il , the device can not perform program and eras e operation in the two "outermost" 4kword boot blocks on both ends of the flash array independently of whet her those blocks were protected or unprotected using the metho d described in "block protection/unprotection". ( ba77 and ba76, ba0 and ba1) the write protected blocks can only be read. this is useful method to preserve an important program data. when the wp /acc pin is asserted at v ih , the device reverts to whether the two outermost 4kword boot blocks were last set to be protected or unprotected. that is, block protection or unprotec tion for these two blocks depends on whether they were last prot ected or unprotected using the method descri bed in "block protection/unprotection". recommend that the wp /acc pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunc- tion. software reset the reset command provides that the bank is reseted to read m ode or erase-suspend-read mode. the addresses are in don't care state. the reset command is vaild between the sequence cycles in an erase command s equence before erasing begins, or in a pro- gram command sequence before programming begins. this resets the b ank in which was operating to read mode. if the device is be erasing or programming, the reset command is invalid until the operation is completed. also, the reset command is valid between the sequence cycles in an autoselect command sequence. in the autosel ect mode, the reset command returns the bank to read mode. if a bank entered the autoselect mode in the erase suspend mode, the reset command returns the bank to erase-suspend-read mode. if dq5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode if the bank was in the erase suspend state. hardware reset the k8p3215uqb offers a reset feature by driving the reset pin to v il . the reset pin must be kept low (v il ) for at least 500ns. when the reset pin is driven low, any operation in progress will be termi nated and the internal state machine will be reset to the standby mode after 20us. if a hardware reset occurs during a pr ogram operation, the data at that particular location will be l ost. once the reset pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. also, note that all the data output pins are tri-stated for the duration of the reset pulse. the reset pin may be tied to the system reset pin. if a system reset occurs during the internal program and erase routine, the device will be automatically reset to the read mode ; this will enable the systems microprocesso r to read the boot-up firmware from the flash memory.
flash memory k8p3215uqb revision 1.1 april 2007 17 power-up protection to avoid initiation of a write cycle during vcc power-up, reset low must be asserted during power-up. after reset goes high, the device is reset to the read mode. low vcc write inhibit to avoid initiation of a write cycle duri ng vcc power-up and power-down, a write cycle is locked out for vcc less than 2.3v. if vcc < v lko (lock-out voltage), the command register and all internal program /erase circuits are disabled. under this condition the device will reset itself to the read mode. subsequent writes will be ignored until the vcc level is greater than v lko . it is the user s responsi- bility to ensure that the control pins are logically correct to prevent unint entional writes when vcc is above 2.3v. write pulse glitch protection noise pulses of less than 5ns(typical) on ce , oe , or we will not initiate a write cycle. logical inhibit writing is inhibited under any one of the following conditions : oe = v il , ce = v ih or we = v ih . to initiate a write, ce and we must be "0", while oe is "1". commom flash memory interface common flash momory interface is contrived to increase the compatibility of host system software. it provides the specific inf orma- tion of the device, such as memory size, word configuration, and electrical featur es. once this information has been obtained, the system software will know which command sets to use to enabl e flash writes, block erases, a nd control the flash component. when the system writes the cfi command(98h) to address 55h in wo rd mode, the device enters the cfi mode. and then if the sys- tem writes the address shown in table 8, the system can read the cfi data. query data are always presented on the lowest-order data outputs(dq0-7) only. in word(x16) mode, the upper data output s(dq8-15) is 00h. to terminate this operation, the system mu st write the reset command. otp block region the otp block feature provides a 256-word flash memory region that enables permanent pa rt identification through an electronic serial number (esn). the otp block is customer lockable and sh ipped with itself unlocked, allo wing customers to untilize the th at block in any manner they choose. indicato r bits dq6 and dq7 are used to indicate th e factory-locked and customer locked status of the part. the data is dq6 = "1" for customer locked and dq7 = "1" for factory locked. the system accesses the otp block through a command sequenc e (see "enter otp block / exit otp block command sequence" at table 6). after the system has written the "enter otp bl ock" command sequence, it may read the otp block by using the addresses (000000h~0000ffh) normally and may check the protection veri fy bit (dq7,dq6) by using t he "autoselect block protec- tion verify" command sequence with otp block address. this mode of operation conti nues until the system issues the "exit otp block" command suquence, a hardware reset or until power is re moved from the device. on power-up, or following a hardware reset, the device reverts to sending commands to main blocks. no te that the accelerated function and unlock bypass modes are no t available when the otp block is enabled. customer lockable in a customer lockable device, the otp block is one-time prog rammable and can be locked only once. note that the accelerated programming and unlock bypass functions ar e not available when programming the otp bl ock. locking operation to the otp block is started by writing the "enter otp bl ock" command sequence, and it can be permanently locked to "1" by issuing the otp protec - tion bit program command sqeunce. once the otp block is locked and verified, the system must wr ite the exit otp block command to return to reading and writing the remainder of the array. otp protection bits otp protection bits prevent programming of the otp block memory area. once set, the otp area are non-modifiable. ? the otp block lock operation must be used with caution since, once locked, there is no procedure available for unlocking and n one of the bits in the otp block space can be modified in any way. ? suspend and resume operation are not supported during otp protec t, nor is otp protect supported during any suspend operation.
flash memory k8p3215uqb revision 1.1 april 2007 18 high voltage block protection block protection and unprotection may also be implemented usi ng programming equipment. the procedure requires high voltage (vid) to be placed on the reset# pin. refer to figure 8 for detai ls on this procedure. note that for block unprotect, all unpro tected blocks must first be protected prior to the first sector write cycle. accelerated program operation accelerated program operation is one of two functions provided by the wp /acc pin. when the wp /acc pin is asserted as v hh , the device automatically enters the unlock bypa ss mode, temporarily unprotecting any prot ected blocks. the system would use a two- cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp /acc pin returns the device to normal operation. recommend that the wp /acc pin must not be asserted at v hh except on accelerated program operation, or the device may be damaged. in addition, the wp /acc pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunction. single word accelerated program operation the system would use two-cycl e program sequence (one-cycle ( xxx - a0h) is for single word program command, and next one- cycle (pa - pd) is for program address and data ). quadruple word accelerated program operation as well as single word accelerated program , the system would use five-cycle program sequence (one-cycle (xxx - a5h) is for qua - druple word program command, and four c ycles are for program address and data). ? only four words programming is possible ? each program address must have the same a20~a2 address ? the device automatically generat es adequate program pulses and ignores other command after program command ? program/erase cycling must be limited below 100cycles for optimum performance. ? read while write mode is not guaranteed requirements : ambient temperature : t a =30 c 10 c
flash memory k8p3215uqb revision 1.1 april 2007 19 figure 8. block group protection & unprotection algorithms block protect algorithm set up block group address block group protect: write 60h to block group address with a6=0,a1=1 a0=0 wait 120 s verify block group protect:write 40h to block group address with a6=0, a1=1,a0=0 read from block group address with a6=0, a1=1,a0=0 data=01h? protect another block group? remove v id from reset write reset command end wait 4 s first write cycle=60h? temporary block group unprotect mode block group unprotect write 60h with a6=1,a1=1 a0=0 wait 3ms verify block group unprotect:write 40h to block group address with a6=1, a1=1,a0=0 read from block group address with a6=1, a1=1,a0=0 data=00h? last block group remove vid from reset write reset command end no increment count count =1000? device failed no yes yes no no yes algorithm increment count count =25? device failed no yes no all block groups protected ? no block group , i= 0 start count = 1 reset =v id yes yes yes no note : all blocks must be protected bef ore unprotect operation is executing. verified ? block group protection ? yes no yes set up next block reset count=1 block unprotect group address
flash memory k8p3215uqb revision 1.1 april 2007 20 table 8. block protection schemes block protection the k8p3215uqb features several levels of block protection, which can di sable both the program and erase operations in certain blocks or block groups: persistent block protection a command block protection method that replaces the old 12 v controlled protection method. password block protection a highly sophisticated protection method t hat requires a password before changes to certain blocks or block groups are permitte d selecting a block protection mode all parts default to operate in the persistent block protection m ode. the customer must then choose if the persistent or passwo rd protection method is most desirable. there are two one-time pr ogrammable non-volatile bits that define which block protection- method will be used. if the persistent block protection method is desired, programming the persis tent block protection mode loc k- ing bit permanently sets the device to the persistent block protection mode. if the pa ssword block protection method is desired , programming the password mode locking bit permanently se ts the device to the password block protection mode. it is not possible to switch between the two protection modes once a locking bit has been set. one of the two modes must be selected when the device is first programmed. this prevents a program or virus from later setting the password mode locking bit , which would cause an unexpected shift from the default persistent block protection mode into the password protection mode. the device is shipped with all blocks u nprotected. optional samsung programming services enable programming and protecting blocks at the factory prior to shipping the devic e. contact your local sales office for details. it is possible to determine whether a block is protec ted or unprotected. see autoselect mode for details. persistent block protection the persistent block protection method replaces the 12 v controlled protection me thod in previous flash devices. this new metho d provides three different block protection states: persistently locked - the bl ock is protected and cannot be changed. dynamically locked - the block is protected and can be changed by a simple command. unlocked - the block is unprotec ted and can be changed by a simple command. to achieve these states, three types of "bits" are used: persistent protection bit persistent protection bit lock persistent block protection mode locking bit persistent protection bit (ppb) a single persistent (non-volatile) protection bit is assigned to a maximum four blocks (see the block address tables for specif ic block protection groupings). all 4 kword boot -block sectors have individual block pers istent protection bits(ppbs) for greater flexi- bility. each ppb is individually modifiable through the ppb write command. dyb ppb ppb lock block state 0 0 0 unprotected-ppb and dyb are changeable 0 0 1 unprotected-ppb not changeable and dyb are changeable 01 0 protected-ppb and dyb are changeable 10 0 11 0 0 1 1 protected-ppb not changeable, dyb is changeable 10 1 11 1
flash memory k8p3215uqb revision 1.1 april 2007 21 the device erases all ppbs in parallel. if any ppb requires erasure, the device must be instructed to preprogram all of the blo ck ppbs prior to ppb erasure. otherwise, a previous ly erased block ppbs can potentially be ov er-erased. the flash device does not have a built-in means of preventi ng block ppbs over-erasure. persistent protection bit lock (ppb lock) the persistent protection bit lock (ppb lo ck) is a global volatile bit. when set to "1", the ppbs cannot be changed. when clear ed "0", the ppbs are changeable. there is only one ppb lock bit per device. the ppb lock is cl eared after power-up or hardware reset. there is no command sequence to unlock the ppb lock. dynamic protection bit (dyb) a volatile protection bit is assigned for each block. after power-up or hardware reset, the contents of all dybs is "0". each d yb is indi- vidually modifiable through the dyb write command. when the parts are first shipped, the ppbs are cleared, the dybs are cleared, and ppb loc k is defaulted to power up in the clea red state - meaning the ppbs are changeable. when the device is firs t powered on the dybs power up cleared (blocks not protected). the protection state for each sector is determined by the logical or of the ppb and the dyb related to that block. for the blocks t hat have the ppbs cleared, the dybs control whether or not the block is protected or unprotected. by issuing the dyb write command sequences, the dybs will be set or cleared, thus placing each block in the protected or unpro- tected state. these are the so-called dynamic locked or unlocked states. they are call ed dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions . this allows software to easily protect blocks against i nadvert- ent changes yet does not prevent the easy removal of protection when changes are needed. the dybs maybe set or cleared as often as needed. the ppbs allow for a more static, and difficult to change, level of protection. the ppbs retain their state across power cycles because they are non-volatile. individual ppbs are set with a command but must all be cleared as a group through a complex sequence of pro- gram and erasing commands. the ppbs are also limited to 100 erase cycles. the ppb lock bit adds an additional level of protection. once all ppbs are progra mmed to the desired settings, the ppb lock may be set to "1". setting the ppb lock disables all program and erase commands to the non-volatile ppbs. in effect, the ppb lock bit locks the ppbs into their current state. the only way to clear the ppb lock is to go through a power cycle. system boot code can dete rmine if any changes to the ppb are needed; for example, to allow new system code to be downloaded. if no changes are needed then the boot code can set the ppb lock to disable any further changes to the ppbs during system operation. the wp#/acc write protect pin adds a final level of hardware pr otection to blocks ba141 and ba140, ba0 and ba1. when this pin is low it is not possible to change the contents of these blocks. these blocks generally hold system boot code. the wp#/acc pin ca n prevent any changes to the boot code that could override the c hoices made while setting up blo ck protection during system initi aliza- tion. for customers who are concerned about maliciou s viruses there is another level of security - the persistently locked state. to persis- tently protect a given block or block group, the ppbs associat ed with that block need to be set to "1". once all ppbs are progr ammed to the desired settings, the ppb lock should be set to "1". sett ing the ppb lock automatically disables all program and erase c om- mands to the non-volatile ppbs. in effect, the ppb lock "freezes" the ppbs into their current state. the only way to clear the ppb lock is to go through a power cycle. it is possible to have blocks that have b een persistently locked, and blocks that are left in the dynamic state. the blocks in the dynamic state are all unprotected. if there is a need to protect some of them, a simple dyb write comm and sequence is all that is neces sary. the dyb write command for the dynamic blocks switch the dybs to signify protected and unprotected, respectively. if there is a need to change the status of the persistently locked blocks, a few mo re steps are required. first, the ppb lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to re flect the desired settings. sett ing the ppb lock bit once again will lock the ppbs , and the device operates normally again. the best protection is ac hieved by executing the ppb lock bit set command early in the boot code, and protect the boot code by hold- ing wp#/acc = vil. table 8 contains all possible combinations of the dyb, ppb, and ppb lock relating to the status of the block. in summary, if the ppb is set, and the ppb lock is set, the bloc k is protected and the protection can not be removed until the next power cycle clears the ppb lock. if the ppb is cleared, the block can be dynamically locked or unlocked. the dyb then controls whether or not the block is protected or unprotected.
flash memory k8p3215uqb revision 1.1 april 2007 22 if the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. a program command to a protected block enables stat us polling for approximately 1us before the device returns to read mode without having modified the contents of the protected block. an erase command to a protected block enables stat us polling for approximately 50 us after which the device returns to read mode without having erased the protected block. the programming of the dyb, ppb, and ppb lock for a given block can be verified by wr iting a dyb/ppb/ppb lock verify command to the device. persistent block protection mode locking bit like the password mode locking bit, a pers istent block protection mode locking bit exists to guarantee that the device remain i n soft- ware block protection. once set, the persistent block protecti on locking bit prevents programmi ng of the password protection mo de locking bit. this guarantees that a hacker could not place the device in password protection mode. password protection mode the password block protection mode method allows an even higher le vel of security than the persistent block protection mode. there are two main differences between the persistent block protection and the password block protection mode: when the device is first powered on, or comes out of a reset cyc le, the ppb lock bit set to the locked state, rather than clear ed to the unlocked state. the only means to clear the ppb lock bit is by writing a unique 64-bit password to the device. the password block protection method is otherwise i dentical to the persistent block protection method. a 64-bit password is the only additional tool utilized in this method. once the password mode locking bit is set, the password is permane ntly set with no means to read, program, or erase it. the pas s- word is used to clear the ppb lock bit. the password unlock co mmand must be written to the flash, along with a password. the flash device internally compares the given password with the pre-programmed password. if they match, the ppb lock bit is cleare d, and the ppbs can be altered. if they do not match, the flash devic e does nothing. there is a built-in 2us delay for each "passw ord check." this delay is intended to thwart any efforts to run a pr ogram that tries all possible combinations in order to crack th e pass- word. password and password mode locking bit in order to select the password block prot ection scheme, the customer must first program the password. the password may be cor- related to the unique electronic serial number (esn) of the partic ular flash device. each esn is different for every flash devi ce; therefore each password should be different for every flash device. whil e programming in the password region, the customer may perform password verify operations. once the desired password is programmed in, the customer must then set the password mode locki ng bit. this operation achieves two objectives: permanently sets the device to operate using the password prot ection mode. it is not possibl e to reverse this function. disables all further commands to the password r egion. all program, and read operations are ignored. both of these objectives are important, and if not carefully cons idered, may lead to unrecoverable errors. the user must be sur e that the password protection method is desired when setting the password mode locking bit. more importantly, the user must be sure that the password is correct when the password mode locking bit is set. due to the fact that read operations are disabled, ther e is no means to verify what the password is afterwards. if the pa ssword is lost after setting the password mode locking bit, there will be no way to clear the ppb lock bit. the password mode locking bit, once set, prevents reading the 64-b it password on the dq bus and further password programming. the password mode locking bit is not erasable. once password mode locking bit is programmed, t he persistent block protection locking bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and verify com - mands (see "password verify command"). the password function works in conjunction with the password mode locking bit, which when set, prevents the password verify command from reading t he contents of the password on the pins of the device. write protect (wp#) the write protect feature provides a hardware method of protecti ng the upper two and lower two blocks without using vid. this f unc- tion is provided by the wp# pin and overrides the previous ly discussed "high voltage bloc k protection" section method.
flash memory k8p3215uqb revision 1.1 april 2007 23 if the system asserts vil on the wp#/acc pi n, the device disables program and erase f unctions in the two outermost 4 kword bloc ks on both ends of the flash array independent of whet her it was previously protected or unprotected. if the system asserts vih on the wp#/acc pin, the device reverts the upper two and lower two blocks to whether they were last s et to be protected or unprotected. that is, block protection or unpr otection for these sectors depends on whether they were last p ro- tected or unprotected using the method described in the "high voltage block protection" section. persistent protection bit lock the persistent protection bit ( ppb) lock is a volatile bit that reflects the state of the password mode locking bit after power -up reset. if the password mode lock bit is also set after a hardware rese t (reset# asserted) or a power-up reset, the only means for clea r- ing the ppb lock bit in password protection mode is to issue the pa ssword unlock command. successf ul execution of the password unlock command clears the ppb lock bit, allowing for block ppbs m odifications. asserting reset#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a "1" when the password mode lock bit is not set. if the password mode locking bit is not set, including persistent protection mode, the ppb lock bit is cleared after power-up o r hard- ware reset. the ppb lock bit is set by issuing the ppb lock bi t set command. once set the only means for clearing the ppb lock bit is by issuing a hardware or power- up reset. the password unlock command is ignored in persistent protection mode. master locking bit set this master locking bit can ensure that protected blocks be permanently unalterable. master locking bit is non-volatile bit. master locking bit controls pr otection status of entire blocks. the usage of the master locking bit command s equence is absolutely required to ensure full protection of data from future alter ations. if master locking bit is set ("1"), entire blocks are permanently protecte d. they are not changed and altered by any future loc k/unlock commands. anyone who uses this fuction needs much attention. because there is no way to return to unlock status. default status of master lock- ing bit is unlock status("0"). if master locking bit sets on unprotected block, the bloc k still are remaining in status of unprotected block. the unprotected block can be protected by protection command.
flash memory k8p3215uqb revision 1.1 april 2007 24 table 9. k8p3215uqb boot block/block addresses for protection / unprotection block a20-a12 block size ba0 000000000 4 kwords ba1 000000001 4 kwords ba2 000000010 4 kwords ba3 000000011 4 kwords ba4 000000100 4 kwords ba5 000000101 4 kwords ba6 000000110 4 kwords ba7 000000111 4 kwords ba8 000001xxx 32 kwords ba9 000010xxx 32 kwords ba10 000011xxx 32 kwords ba11-ba14 0001xxxxx 128 (4x32) kwords ba15-ba18 0010xxxxx 128 (4x32) kwords ba19-ba22 0011xxxxx 128 (4x32) kwords ba23-ba26 0100xxxxx 128 (4x32) kwords ba27-ba30 0101xxxxx 128 (4x32) kwords ba31-ba34 0110xxxxx 128 (4x32) kwords ba35-ba38 0111xxxxx 128 (4x32) kwords ba39-ba42 1000xxxxx 128 (4x32) kwords ba43-ba46 1001xxxxx 128 (4x32) kwords ba47-ba50 1010xxxxx 128 (4x32) kwords ba51-ba54 1011xxxxx 128 (4x32) kwords ba55-ba58 1100xxxxx 128 (4x32) kwords ba59-ba62 1101xxxxx 128 (4x32) kwords ba63-ba66 1110xxxxx 128 (4x32) kwords ba67 111100xxx 32 kwords ba68 111101xxx 32 kwords ba69 111110xxx 32 kwords ba70 111111000 4 kwords ba71 111111001 4 kwords ba72 111111010 4 kwords ba73 111111011 4 kwords ba74 111111100 4 kwords ba75 111111101 4 kwords ba76 111111110 4 kwords ba77 111111111 4 kwords
flash memory k8p3215uqb revision 1.1 april 2007 25 table 10. block protection command sequences legend: dyb = dynamic protection bit ow = address (a7:a0) is (00011010) pd[3:0] = password data (1 of 4 portions) ppb = persistent protection bit pwa = password address. a1:a0 selects portion of password. pwd = password data being verified. pl = password protection mode lock address (a7:a0) is (00001010) rd(0) = read data dq0 for protection indicator bit. rd(1) = read data dq1 for ppb lock status. ba = block address where security command applies. address bits amax:a12 uni quely select any block. bl = persistent protection mode lock address (a7:a0) is (00010010) wp = ppb address (a7:a0) is (00000010) command sequence cycl 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle 7th cycle password program(1,2) add 4 555h 2 a a h 555h xx[0-3]h dat aah 55h 38h pd[0-3] password verify(2,4,5) add 4 555h 2aah 555h pwa[0-3] dat aah 55h c8h pwd[0-3] password unlock(3,6,7) add r 7 555h 2aah 555h pwa[0] pwa[1] pwa[2] pwa[3] dat aah 55h 28h pwd[0] pwd[1] pwd[2] pwd[3] ppb program(1,2,8) add r 6 5 5 5 h 2 a a h 5 5 5 h ( b a ) w p ( b a ) w p ( b a ) w p dat aah 55h 60h 68h 48h rd(0) master locking bit set add r 3 555h 2aah 555h dat a aah 55h f1h ppb status add r 4 555h 2aah 555h (ba)wp dat aah 55h 90h rd(0) all ppb erase(1,2,9,10) add 6 555h 2aah 555h wp (ba) (ba)wp dat aah 55h 60h 60h 40h rd(0) ppb lock bit set add 3 555h 2aah 555h dat aah 55h 78h ppb lock bit status(11) add 4 555h 2aah 555h ba dat aah 55h 58h rd(1) dyb write(3) add 4 555h 2aah 555h ba dat aah 55h 48h x1h dyb erase(3) add 4 555h 2aah 555h ba dat aah 55h 48h x0h dyb status(2) add 4 555h 2aah (da)555h ba dat aah 55h 58h rd(0) ppmlb program(1,2,8) add 6 555h 2aah 555h pl pl pl dat aah 55h 60h 68h 48h rd(0) ppmlb status(1) add 5 555h 2aah 555h pl pl dat aah 55h 60h 48h rd(0) spmlb program(1,2,8) add 6 555h 2aah 555h bl bl bl dat aah 55h 60h 68 48 rd(0) spmlb status(1) add 5 555h 2aah 555h bl bl dat aah 55h 60h 48 rd(0)
flash memory k8p3215uqb revision 1.1 april 2007 26 x = don?t care ppmlb = password protection mode locking bit spmlb = persistent protection mode locking bit notes: ? see the description of bus operations. ? all values are in hexadecimal. ? shaded cells in table denote read cycles . all other cycles are write operations. ? during unlock and command cycles, when lower address bits ar e 555 or 2aah as shown in table, address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 1. the reset command returns device to reading array. 2. cycle 4 programs the addressed lock ing bit. cycles 5 and 6 validate bit has been fully programmed when dq0 = 1. if dq0 = 0 in cycle 6, program command must be issued and verified again. 3. data is latched on the rising edge of we#. 4. entire command sequence must be entered for each portion of password. 5. command sequence returns ffh if ppmlb is set. 6. the password is written over four consecutive cycles, at addresses 0-3. 7. 2us timeout is required betw een any two portions of password. 8. 100us timeout is required between cycles 4 and 5. 9. 1.2 ms timeout is required between cycles 4 and 5. 10. cycle 4 erases all ppbs. cycles 5 and 6 validate bits have been fully erased when dq0 = 0. if dq0 = 1 in cycle 6, erase command must be issued and verified again. before issuing erase command, all ppbs s hould be programmed to prevent ppb overerasure. 11. dq1 = 1 if ppb locked, 0 if unlocked.
flash memory k8p3215uqb revision 1.1 april 2007 27 table 11. common flash memory interface code description addresses (word mode) data query unique ascii string "qry" 10h 11h 12h 0051h 0052h 0059h primary oem command set 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = none exists) 17h 18h 0000h 0000h address for alternate oem extended table (00h = none exists) 19h 1ah 0000h 0000h vcc min. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1bh 0027h vcc max. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1ch 0036h vpp min. voltage(00h = no vpp pin present) 1dh 0000h vpp max. voltage(00h = no vpp pin present) 1eh 0000h typical timeout per single word write 2 n us 1fh 0003h typical timeout for min. size buffer write 2 n us(00h = not supported) 20h 0000h typical timeout per individual block erase 2 n ms 21h 0009h typical timeout for full chip erase 2 n ms(00h = not supported) 22h 0000h max. timeout for word write 2 n times typical 23h 0004h max. timeout for buffer write 2 n times typical 24h 0000h max. timeout per individual block erase 2 n times typical 25h 0004h max. timeout for full chip erase 2 n times typical(00h = not supported) 26h 0000h device size = 2 n byte 27h 0016h flash device interface description 28h 29h 0001h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block regions within device 2ch 0003h erase block region 1 information 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 2 information 31h 32h 33h 34h 003dh 0000h 0000h 0001h erase block region 3 information 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 4 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h
flash memory k8p3215uqb revision 1.1 april 2007 28 table 11. common flash memory interface code description addresses (word mode) data query-unique ascii string "pri" 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0030h minor version number, ascii 44h 0030h address sensitive unlock(bits 1-0) 0 = required, 1= not required silcon revision number(bits 7-2) 45h 0000h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 46h 0002h block protect 00 = not supported, 01 = supported 47h 0001h block temporary unprotect 00 = not supported, 01 = supported 48h 0001h block protect/unprotect scheme, 00 = not supported, 01 = supported 49h 0001h simultaneous operation 00 = not supported, 01 = supported 4ah 0001h burst mode type 00 = not supported, 01 = supported 4bh 0000h page mode type 00 = not supported, 01 = 4 word page 02 = 8 word page 4ch 0002h acc(acceleration) supply minimum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 4dh 0085h acc(acceleration) supply maximum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 4eh 0095h top/bottom boot block flag 02h = bottom boot device, 03h = top boot device, 04h = top and bottom device 4fh 0004h
flash memory k8p3215uqb revision 1.1 april 2007 29 device status flags the k8p3215uqb has means to indicate its status of operation in the bank where a program or erase operation is in processes. address must include bank address being excuted internal routine operation. the status is indicated by raising the device statu s flag via corresponding dq pins or the ry/ by pin. the corresponding dq pins are dq7, dq6, dq5, dq3 and dq2. the statuses are as follows : table 12. hardware sequence flags notes : 1. dq2 will toggle when the device performs successive read operations from the erase/program suspended block. 2. if dq5 is high (exceeded timing limits), successive reads from a problem block will cause dq2 to toggle. status dq7 dq6 dq5 dq3 dq2 ry/by in progress programming dq7 toggle 0 0 1 0 block erase or chip erase 0 toggle 0 1 toggle 0 erase suspend read erase suspended block 1100 toggle (note 1) 1 erase suspend read non-erase sus- pended block data data data data data 1 erase suspend program non-erase sus- pended block dq7 toggle 0 0 1 0 program suspend read program sus- pended block dq7100 toggle (note 1) 1 program suspend read non-program sus- pended block data data data data data 1 exceeded time limits programming dq7 toggle 1 0 no toggle 0 block erase or chip erase 0 toggle 1 1 (note 2) 0 erase suspend program dq7 toggle 1 0 no toggle 0 dq7 : data polling when an attempt to read the device is made while executing the in ternal program, the complement of the data is written to dq7 a s an indication of the routine in progress. when the routine is co mpleted an attempt to access to the device will produce the tru e data written to dq7. when a user attempts to read the block being er ased, dq7 will be low. if the dev ice is placed in the erase/prog ram suspend mode, the status can be detected via the dq7 pin. if the system tries to read an address which belongs to a block that is being erase suspended, dq7 will be high. and, if the system tries to read an address which belongs to a block that is being pro gram suspended, the output will be the true data of dq7 itself. if a non-erase-suspended or non-program-suspended block address is read, the device will produce the true data to dq7. if an attempt is made to program a protected block, dq7 outputs complements the data for approximately 1 s and the device then returns to the read mode without changing data in the block. if an attempt is made to erase a protected block, dq7 outputs complement dat a in approximately 100us and the device then returns to the read mode without erasing the data in the block. dq6 : toggle bit toggle bit is another option to detect whether an internal routine is in progress or completed. once the device is at a busy st ate, dq6 will toggle. toggling dq6 will stop after the device completes its internal routine. if the device is in the erase/program suspend mode, an attempt to read an address that belongs to a block that is being erased or programmed w ill produce a high output of dq 6. if an address belongs to a block that is not being erased or progr ammed, toggling is halted and valid data is produced at dq6. if an attempt is made to program a protected bl ock, dq6 toggles for approxim ately 1us and the device then returns to the read mode without changing the data in the block. if an attempt is made to erase a protected block, dq6 toggles for approximately 100 s and the device then returns to the read mode without erasing the dat a in the block. #oe or #ce should be toggled in each toggle bi t sta- tus read.
flash memory k8p3215uqb revision 1.1 april 2007 30 ry/by : ready/busy the k8p3215uqb has a ready / busy output that indicates either the completion of an operation or the status of internal algorithms. if the output is low, the device is busy with either a program or an erase operation. if the output is high, the device is read y to accept any read/write or erase operation. when the ry/ by pin is low, the device will not accept any additional program or erase commands with the exception of the erase suspend command. if the k8p3215uqb is placed in an erase suspend mode, the ry/ by output will be high. for programming, the ry/ by is valid (ry/ by = 0) after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, ry/ by is also valid after the rising edge of we pulse in the six write pulse sequence. for block erase, ry/ by is also valid after the rising edge of the sixth we pulse. the pin is an open drain output, allowing two or more ready/ busy outputs to be or-tied. an appropriate pull-up resistor is required for proper operation. rp = v cc ready / busy open drain output device gnd vcc (max.) - v ol (max.) i ol + i l = 3.2 v 2.1ma + i l where i l is the sum of the input currents of all devices tied to the ready / busy pin. rp dq5 : exceed timing limits if the internal program/erase routine extends beyond the timing limits, dq5 will go high, indi cating program/erase failure. dq3 : block erase timer the status of the multi-block erase operation can be detected via the dq3 pin. dq3 will go high if 50 s of the block erase time win- dow expires. in this case, the internal erase routine will initia te the erase operation.therefore, the device will not accept f urther write commands until the erase operation is complet ed. dq3 is low if the block erase time wi ndow is not expired. within the block era se time window, an additional block erase command (30h) can be accepted. to confirm that the block erase command has been accepted, the software may check the status of dq3 following each block erase command. dq2 : toggle bit 2 the device generates a toggling pulse in dq2 only if an internal erase routine or an erase/program suspend is in progress. when the device executes the internal erase rout ine, dq2 toggles only if an erasing bank is read. although the internal erase routin e is in the exceeded time limits, dq2 toggles onl y if an erasing block in the exceeded time limits is read. when the device is in th e erase/program suspend mode, dq2 toggles only if an address in the erasing or programming block is read. if a non-erasing or non - programmed block address is read during the erase/program suspend mode, then dq2 will produce valid data. dq2 will go high if the user tries to program a non-erase sus pend block while the device is in the erase suspend mode. #oe or #ce should be toggled in each toggle bit status read.
flash memory k8p3215uqb revision 1.1 april 2007 31 start dq7 = data ? no dq5 = 1 ? fail pass yes figure 9. data polling algorithms dq7 = data ? no no yes read(dq0~dq7) valid address read(dq0~dq7) valid address yes figure 10. toggle bit algorithms start dq6 = toggle ? no dq5 = 1 ? fail pass no dq6 = toggle ? yes yes no read twice(dq0~dq7) valid address read(dq0~dq7) valid address yes read(dq0~dq7) valid address
flash memory k8p3215uqb revision 1.1 april 2007 32 dc characteristics recommended operating conditions ( voltage reference to gnd ) parameter symbol min typ. max unit supply voltage v cc 2.7 3.0 3.6 v supply voltage v ss 000v absolute maximum ratings notes : 1. minimum dc voltage is -0.5v on input/ output pins. during tran sitions, this level may fall to -2.0v for periods <20ns. maxim um dc voltage on input / output pins is vcc+0.5v which, during transitions, may overshoot to vcc+2.0v for periods <20ns. 2. minimum dc voltage is -0.5v on a9, reset and wp /acc pins. during transitions, this level may fall to -2.0v for periods <20ns. maximum dc voltage on a9, reset , wp /acc pins is 9.5v which, during transitions , may overshoot to 14.0v for periods <20ns. 3. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss vcc vcc -0.5 to +4.0 v a9, reset v in -0.5 to +9.5 wp /acc -0.5 to +9.5 all other pins -0.5 to +2.5 temperature under bias commercial t bias -10 to +125 c extended -25 to +125 storage temperature t stg -65 to +150 c short circuit output current i os 5ma operating temperature t a (commercial 0 to +70 c t a (extended temp.) -25 to + 85 c parameter sym- bol test conditions min typ max unit input leakage current i li vin=vss to vcc, vcc=vccmax ? 1.0 - + 1.0 a a9,reset input leakage current i lit vcc=vccmax, a9, reset =9.5v --35 a wp /acc input leakage current i liw vcc=vccmax, wp /acc=9.5v - - 35 a output leakage current i lo vout=vss to vcc,vcc=vcc- max,oe =vih ? 1.0 - + 1.0 a active read current (1) i cc 1oe =vih, vcc=vccmax 10mhz - 45 55 ma 5mhz - 20 30 active write current (2) i cc 2ce =v il , oe =v ih, we =v il -1530ma read while program current (3) i cc 3ce =v il , oe =v ih (@10mhz) -3555ma read while erase current (3) i cc 4ce =v il , oe =v ih (@10mhz) -3555ma program while erase suspend current i cc 5ce =v il , oe =v ih -1535ma page read current i cc 6oe =v ih, 8 word page read -1015ma acc accelerated program current i acc ce =v il , oe =v ih -1530ma standby current i sb 1 ce , reset , wp /acc= v io 0.3 -1530 a standby current during reset i sb 2 reset = vss 0.3 -1530 a automatic sleep mode i sb 3 v ih =v io 0.3v, v il =v ss 0.2v -1530 a input low level v il vio=1.65~1.95v(2.7~3.6v) -0.4(-0.5) - 0.4 (vccx0.2) v input high level v ih vio=1.65~1.95v(2.7~3.6v) vio -0.4 (vccx0.8) - vio+0.4 (vcc+0.3) v voltage for wp /acc block tempo- rarily unprotect and program accelera- tion (4) v hh vcc = 3 .0v 0.15v 8.5 - 9.5 v
flash memory k8p3215uqb revision 1.1 april 2007 33 ac test condition parameter value input pulse levels 0v to vcc input rise and fall times(vio=1.8,3.0v) 5ns input and output timing levels vcc/2 output load c l = 30pf 0v vcc vcc/2 vcc/2 input pulse and test point input & output test point notes : 1. the i cc current listed includes both the dc operating current and the frequency dependent component(at 10 mhz). 2. i cc active during internal routine(program or erase) is in progress. 3. i cc active during read while write is in progress. 4. the high voltage ( v hh or v id ) must be used in the range of vcc = 3.0v 0.15v 5. not 100% tested. 6. typical value are measured at vcc = 3.0v,t a =25 c , not 100% tested. capacitance (t a = 25 c, v cc = 3.0v, f = 1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 10 pf output capacitance c out v out =0v - 10 pf control pin capacitance c in2 v in =0v - 10 pf parameter symbol test conditions min typ max unit voltage for autoselect and block protect (4) v id vcc = 3.0v 10% 8.5 - 9.5 v output low level v ol iol =100ua,vcc=vccmin, vio=1.65~1.95v -0.1v iol =2.0ma,vcc=vccmin, vio=2.7~3.6v -0.4v output high level v oh ioh = -100ua, vcc=vccmin, vio=1.65~1.95v vio-0.1 - - v ioh = -2.0ma, vcc=vccmin, vio=2.7~3.6v 2.4 --v low vcc lock-out voltage (5) v lko 2.3 - 2.5 v output load * cl= 30pf including scope c l device and jig capacitance ac characteristics read operations note : 1. not 100% tested. parameter symbol v cc =2.7v~3.6v unit 4a 4b 4c 4d min max min max min max min max read cycle time (1) t rc 55 - 60 - 65 - 70 - ns address access time t aa - 55 - 60 - 65 - 70 ns chip enable access time t ce - 55 - 60 - 65 - 70 ns output enable time t oe - 20 - 25 - 30 - 30 ns page read cycle time (1) t prc 20 - 25 - 25 - 30 - ns page address access time t pa - 20 - 25 - 25 - 30 ns ce & oe disable time (1) t df - 16 - 16 - 16 - 16 ns output hold time from address, ce or oe (1) t oh 5 -5-5-5- ns
flash memory k8p3215uqb revision 1.1 april 2007 34 alternate we controlled write notes : 1. not 100% tested. 2. the duration of the program or erase operation va ries and is calculated in the internal algorithms. parameter symbol v cc =2.7v ~ 3.6v unit 4a 4b 4c 4d min max min max min max min max write cycle time (1) t wc 55 - 60 - 65 - 70 - ns address setup time t as 0 - 0-0-0-ns t aso 15 - 15 - 15 - 15 - ns address hold time t ah 30 - 35 - 35 - 35 - ns t aht 0 - 0-0-0-ns data setup time t ds 25 - 30 - 30 - 30 - ns data hold time t dh 0 - 0-0-0-ns output enable setup time (1) t oes 0 - 0-0-0-ns output enable hold read (1) t oeh1 0 - 0-0-0-ns toggle and data polling (1) t oeh2 10 - 10 - 10 - 10 - ns ce setup time t cs 0 - 0-0-0-ns ce hold time t ch 0 - 0-0-0-ns write pulse width t wp 35 - 35 - 35 - 35 - ns write pulse width high t wph 20 - 25 - 25 - 25 - ns programming operation t pgm 6(typ.) 6(typ) 6(typ.) 6(typ.) s accelerated programming operation t accpgm 6(typ.) 6(typ) 6(typ.) 6(typ.) s accelerated quad word programming operation t accpgm_q uad 1.5(typ.) 1.5(typ.) 1.5(typ.) 1.5(typ.) s block erase operation (2) t bers 0.7(typ.) 0.7(typ) 0.7(typ.) 0.7(typ.) sec v cc set up time t vcs 50 - 50 - 50 - 50 - s write recovery time from ry/ by t rb 0 - 0-0-0-ns reset high time before read t rh 50 - 50 - 50 - 50 - ns reset to power down time t rpd 20 - 20 - 20 - 20 - s program/erase valid to ry/by delay t busy 35 90 35 90 35 90 35 90 ns v id rising and falling time t vid 500 - 500 - 500 - 500 - ns reset pulse width t rp 500 - 500 - 500 - 500 - ns reset low to ry/by high t rrb - 20 - 20 - 20 - 20 s reset setup time for tempo- rary unprotect t rsp 4 - 4-4-4- s reset low setup time t rsts 500 - 500 - 500 - 500 - ns reset high to address valid t rstw 200 - 200 - 200 - 200 - ns read recovery time before write t ghwl 0 - 0-0-0-ns ce high during toggling bit poll- ing t ceph 20 - 20 - 20 - 20 - ns oe high during toggling bit poll- ing t oeph 10 - 10 - 10 - 10 - ns ac characteristics write(erase/program)operations
flash memory k8p3215uqb revision 1.1 april 2007 35 ac characteristics write(erase/program)operations alternate ce controlled writes notes : 1. not 100% tested. 2.this does not include the preprogramming time. parameter symbol v cc =2.7v ~ 3.6v unit 4a 4b 4c 4d min max min max min max min max write cycle time (1) t wc 55 - 60 - 65 - 70 - ns address setup time t as 0-0-0-0-ns address hold time t ah 30 - 35 - 35 - 35 - ns data setup time t ds 25 - 30 - 30 - 30 - ns data hold time t dh 0-0-0-0-ns output enable setup time (1) t oes 0-0-0-0-ns out- put enable hold read (1) t oeh1 0-0-0-0-ns toggle and data polling (1) t oeh2 10 - 10 - 10 - 10 - ns we setup time t ws 0-0-0-0-ns we hold time t wh 0-0-0-0-ns ce pulse width t cp 35 - 40 - 40 - 40 - ns ce pulse width high t cph 20 - 25 - 25 - 25 - ns programming operation t pgm 6(typ.) 6(typ) 6(typ.) 6(typ.) s accelerated programming operation t accpgm 6(typ.) 6(typ) 6typ.) 6(typ.) s accelerated quad word programming operation t accpgm_qua d 1.5(typ.) 1.5(typ.) 1.5(typ.) 1.5(typ.) s block erase operation (2) t bers 0.7(typ.) 0.7(typ) 0.7typ.) 0.7(typ.) sec erase and program performance notes : 1. 25 c, v cc = 3.0v 100,000 cycles, typical pattern . 2. system-level overhead is defined as the time required to execute the four bus cycle command necessary to program each word . in the preprogramming step of the internal erase routine, all words are programmed to 00h before erasure. parameter limits unit comments min typ max block erase time - 0.7 2 sec excludes 00h programming prior to erasure chip erase time - 39 62.4 sec word programming time - 6 100 s excludes system-level overhead accelerated word program time - 6 100 s accelerated quad word program time - 1.5 - s chip programming time ( normal) - 12.6 25.2 sec chip programming time ( acc. quad) -3-sec erase/program endurance 100,000 - - cycles minimum 100,000 cycles guaranteed
flash memory k8p3215uqb revision 1.1 april 2007 36 conventional read operations note : 1. not 100% tested. parameter symbol 4a 4b 4c 4d unit min max min max min max min max read cycle time t rc 55 - 60 - 65 - 70 - ns address access time t aa - 55 - 60 - 65 - 70 ns chip enable access time t ce - 55 - 60 - 65 - 70 ns output enable time t oe - 20 - 25 - 30 - 30 ns ce & oe disable time (1) t df - 16 - 16 - 16 - 16 ns output hold time from address, ce or oe t oh 5-5-5-5-ns oe hold time t oeh 010010010010ns switching waveforms oe address t ce t oeh ce outputs we high-z output valid t rc address stable t aa t oe t oh high-z t df ry/by high figure 11. conventional read operation timings
flash memory k8p3215uqb revision 1.1 april 2007 37 ce a3 to a20 a0 to a2 output oe t rc same page addresses we aa ab ac ad t prc t aa t ce t oe t oeh t pa t pa t oh t oh da db dc dd t df high-z note : 1. not 100% tested. parameter symbol 4a 4b 4c 4d unit min max min max min max min max read cycle time t rc 55 - 60 - 65 - 70 - ns page read cycle time t prc 20 - 25 - 25 - 30 - ns address access time t aa -55-60-65-70ns page address access time t pa -20-25-25-30ns chip enable access time t ce -55-60-65-70ns output enable time t oe -20-25-30-30ns ce & oe disable time (1) t df -16-16-16-16ns output hold time from address, ce or oe t oh 5-5-5-5-ns oe hold time t oeh 0-0-0-0-ns page read operations switching waveforms t oh figure 12. page read operation timings
flash memory k8p3215uqb revision 1.1 april 2007 38 hardware reset/read operations switching waveforms reset address ce outputs high-z t rc address stable t aa t ce t oh t rh t rh t rp output valid parameter symbol 4a 4b 4c 4d unit min max min max min max min max read cycle time t rc 55 - 60 - 65 - 70 - ns address access time t aa - 55 - 60 - 65 - 70 ns chip enable access time t ce - 55 - 60 - 65 - 70 ns output hold time from address, ce or oe t oh 5-5-5-5-ns reset pulse width t rp 500 - 500 - 500 - 500 - ns reset high time before read t rh 50 - 50 - 50 - 50 - ns figure 13. hardware reset/read operation timings
flash memory k8p3215uqb revision 1.1 april 2007 39 alternate we controlled program operations switching waveforms parameter symbol 4a 4b 4c 4d unit min max min max min max min max write cycle time t wc 55 - 60 - 65 - 70 - ns address setup time t as 0-0-0-0-ns address hold time t ah 30 - 35 - 35 - 35 - ns data setup time t ds 25 - 30 - 30 - 30 - ns data hold time t dh 0-0-0-0-ns ce setup time t cs 0-0-0-0-ns ce hold time t ch 0-0-0-0-ns oe setup time t oes 0-0-0-0-ns write pulse width t wp 35 - 35 - 35 - 35 - ns write pulse width high t wph 20 - 25 - 25 - 25 - ns programming operation t pgm 6(typ.) 6(typ) 6(typ.) 6(typ.) us accelerated programming operation t accpgm 6(typ.) 6(typ) 6(typ.) 6(typ.) s read cycle time t rc 55 - 60 - 65 - 70 - ns chip enable access time t ce - 55 - 60 - 65 - 70 ns output enable time t oe - 20 - 25 - 30 - 30 ns ce & oe disable time t df - 16 - 16 - 16 - 16 ns output hold time from address, ce or oe t oh 5-5-5-5-ns program/erase valid to ry/ by delay t busy 35 90 35 90 35 90 35 90 ns recovery time from ry/by t rb 0-0-0-0-ns notes : 1. dq7 is the output of the complement of the data written to the device. 2. dout is the output of the data written to the device. 3. pa : program address, pd : program data 4. the illustration shows the last two cycles of the program command sequence. oe address t cs ce data we t ah t oh t df t as t rc t oe t ce t ds t dh t wp t oes t pgm status dout 555h pa pa a0h data polling t ch pd t wph ry/by t busy t rb t wc figure 14. alternate we controlled program operation timings alternate we controlled program operations
flash memory k8p3215uqb revision 1.1 april 2007 40 alternate ce controlled program operations switching waveforms notes : 1. dq7 is the output of the complement of the data written to the device. 2. dout is the output of the data written to the device. 3. pa : program address, pd : program data 4. the illustration shows the last two cy cles of the program command sequence. parameter symbol 4a 4b 4c 4d unit min max min max min max min max write cycle time t wc 55 - 60 - 65 - 70 - ns address setup time t as 0-0-0-0-ns address hold time t ah 30 - 35 - 35 - 35 - ns data setup time t ds 25 - 30 - 30 - 30 - ns data hold time t dh 0-0-0-0-ns oe setup time t oes 0-0-0-0-ns we setup time t ws 0-0-0-0-ns we hold time t wh 0-0-0-0-ns ce pulse width t cp 35 - 40 - 40 - 40 - ns ce pulse width high t cph 20 - 25 - 25 - 25 - ns programming operation t pgm 6(typ.) 6(typ) 6(typ.) 6(typ.) s accelerated program- ming operation t accpgm 6(typ.) 6(typ) 6(typ.) 6(typ.) s program/erase valid to ry/by delay t busy 35 90 35 90 35 90 35 90 ns recovery time from ry/ by t rb 0-0-0-0-ns oe address we data ce t ah t as t ds t dh t cp t oes a0h 555h pa pa status dout data polling t cph t ws t pgm ry/by t busy t rb pd t wc figure 15. alternate ce controlled program operation timings
flash memory k8p3215uqb revision 1.1 april 2007 41 parameter symbol 4a 4b 4c 4d unit min max min max min max min max write cycle time t wc 55-60-65-70-ns address setup time t as 0-0-0-0-ns address hold time t ah 30-35-35-35-ns data setup time t ds 25-30-30-30-ns data hold time t dh 0-0-0-0-ns oe setup time t oes 0-0-0-0-ns ce setup time t cs 0-0-0-0-ns write pulse width t wp 35-35-35-35-ns write pulse width high t wph 20-25-25-25-ns read cycle time t rc 55-60-65-70-ns v cc set up time t vcs 50-50-50-50- s switching waveforms chip/block erase operations oe address t cs ce data we t ah t as t rc t ds t dh 80h aah aah 55h 30h 10h for chip erase 555h 2aah 555h 555h 2aah ba 555h for chip erase t wph t wp t oes 55h ry/by t wc t vcs vcc note : ba : block address figure 16. chip/block erase operation timings
flash memory k8p3215uqb revision 1.1 april 2007 42 read while write operations switching waveforms parameter symbol 4a 4b 4c 4d unit min max min max min max min max write cycle time t wc 55 - 60 - 65 - 70 - ns write pulse width t wp 35 - 35 - 35 - 35 - ns write pulse width high t wph 20 - 25 - 25 - 25 - ns address setup time t as 0-0-0-0-ns address hold time t ah 30 - 35 - 35 - 35 - ns data setup time t ds 25 - 30 - 30 - 30 - ns data hold time t dh 0-0-0-0-ns read cycle time t rc 55 - 60 - 65 - 70 - ns chip enable access time t ce - 55 - 60 - 65 - 70 ns address access time t aa - 55 - 60 - 65 - 70 ns output enable access time t oe - 20 - 25 - 30 - 30 ns oe setup time t oes 0-0-0-0-ns oe hold time t oeh 10 - 10 - 10 - 10 - ns ce & oe disable time t df - 16 - 16 - 16 - 16 ns address hold time t aht 30 - 35 - 35 - 35 - ns ce high during toggle bit polling t ceph 20 - 20 - 20 - 20 - ns note : this is an example in the program-cas e of the read while write function. da1 : address of bank1, da2 : address of bank 2 pa = program address at one bank , ra = read address at the other bank, pd = program data in , rd = read data out oe ce dq we t rc read command command read read read t ah t aa t ce t as t aht t as t ceph t oe t oes t wp t oeh t df t ds t dh t df da1 da2 da1 da1 da2 da2 (555h) (pa) (pa) valid output valid output valid input valid output valid input status address (a0h) (pd) t rc t rc t rc t wc t wc figure 17. read while write operation timings
flash memory k8p3215uqb revision 1.1 april 2007 43 oe data polling during internal routine operation t ce t oeh ce dq7 we switching waveforms t oe high-z t df note : *dq7=vaild data (the device has completed the internal operation). dq7 *dq7 = valid data t oh t pgm or t bers parameter symbol 4a 4b 4c 4d unit min max min max min max min max program/erase valid to ry/by delay t busy 35 90 35 90 35 90 35 90 ns chip enable access time t ce - 55 - 60 - 65 - 70 ns output enable time t oe - 20 - 25 - 30 - 30 ns ce & oe disable time t df - 16 - 16 - 16 - 16 ns output hold time from address, ce or oe t oh 5-5-5-5-ns oe hold time t oeh 10 - 10 - 10 - 10 - ns high-z valid data dq0-dq6 data in data in we ry/by timing diagram during program/erase operation the rising edge of the last we signal ce ry/by t busy entire progrming or erase operation status data figure 18. data polling during internal routine operation timings figure 19. ry/by timing diagram during program/erase operation timings
flash memory k8p3215uqb revision 1.1 april 2007 44 t dh parameter symbol 4a 4b 4c 4d unit min max min max min max min max output enable access time t oe - 20 - 25 - 30 - 30 ns oe hold time t oeh 10 - 10 - 10 - 10 - ns address hold time t aht 30 - 35 - 35 - 35 - ns address setup t aso 55 - 55 - 55 - 55 - ns address setup time t as 0-0-0-0-ns data hold time t dh 0-0-0-0-ns ce high during toggle bit polling t ceph 20 - 20 - 20 - 20 - ns oe high during toggle bit polling t oeph 10 - 10 - 10 - 10 - ns toggle bit during intern al routine operation switching waveforms ce address* oe dq6/dq2 we ry/by data in t aht t aht t aso t as t ceph t oeh t oeph status data t o e status data status data array data out note : address for the write operation must include a bank address (a19~a20) where the data is written. dq 6 we dq 2 enter embedded erasing erase suspend enter erase suspend program erase suspend program erase resume erase erase suspend read erase erase complete erase suspend read note : dq2 is read from the erase-suspended block. toggle dq 2 and dq 6 with oe or ce figure 20. toggle bit during internal routine operation timings
flash memory k8p3215uqb revision 1.1 april 2007 45 reset timing diagram reset t rp switching waveforms power-up and reset timing diagram parameter sym- bol 4a 4b 4c 4d unit min max min max min max min max reset pulse width t rp 500 - 500 - 500 - 500 - ns reset low to valid data (during internal routine) t ready -20-20-20-20 s reset low to valid data (not during internal routine) t ready - 500 - 500 - 500 - 500 ns reset high time before read t rh 50-50-50-50-ns ry/by recovery time t rb 0-0-0-0-ns reset high to address valid t rstw 200 - 200 - 200 - 200 - ns reset low set-up time t rsts 500 - 500 - 500 - 500 - ns ce or oe ry/by t ready t rb reset ce or oe ry/by t rh t ready t rp reset timings not during internal routine reset timings during internal routine high reset t aa vcc address data t rsts figure 21. power-up and reset timing diagram
flash memory k8p3215uqb revision 1.1 april 2007 46 block group protect & unprotect operations switching waveforms ce temporary block group unprotect program or erase command sequence reset we t rsp ry/by t vid v id v ss ,v il , or v ih v ss ,v il , or v ih t rrb t vid bga,a6 a1,a0 reset ce we data oe v ss ,v il , 60h 60h 40h status* block group protect / unprotect verify 1 s block group protect:120 s block group unprotect:3ms notes : block group protect (a6= v il , a1= v ih , a0= v il ) , status=01h block group unprotect (a6= v ih , a1= v ih , a0= v il ) , status=00h bga = block group address (a12 ~ a20) ry/by v id valid valid valid t busy t rb or v ih v ss ,v il , or v ih
flash memory k8p3215uqb revision 1.1 april 2007 47 switching waveforms figure 22. unlock bypass operation timings ce oe address v pp we dq0-dq15 1us t vps v il or v ih v id t vpp pa don?t care a0h pd don?t care ce oe address v pp we dq0-dq15 1us t vps v il or v ih v id t vpp ba don?t care 80h 30h don?t care 555h for chip erase 10h for chip erase unlock bypass program operations(accelerated program) unlock bypass block erase operations notes: 1. v pp can be left high for subsequent programming pulses. 2. use setup and hold times from conventional program operations. 3. unlock bypass program/erase commands can be used when the v id is applied to vpp. don?t care don?t care
flash memory k8p3215uqb revision 1.1 april 2007 48 figure 23. quad word accelerated program operation timings ce oe address v pp we dq15-dq0 1us t vps v il or v ih v id t vpp don?t care quad word accelerated program notes: 1. v pp can be left high for subsequent programming pulses. 2. use setup and hold times from conventional program operations. 3. quad word acelerate program commands can be used when the v id is applied to vpp. switching waveforms t accpgm_quad a5h pa1 pd1 pa2 pd2 pa3 pd3 pa4 pd4 don?t care va va complete
flash memory k8p3215uqb revision 1.1 april 2007 49 table 13. block architecture ( k8p3215uqb ) bank block block size (x16) address range bank 3 ba77 4 kwords 1ff000h-1fffffh ba76 4 kwords 1fe000h-1fefffh ba75 4 kwords 1fd000h-1fdfffh ba74 4 kwords 1fc000h-1fcfffh ba73 4 kwords 1fb000h-1fbfffh ba72 4 kwords 1fa000h-1fafffh ba71 4 kwords 1f9000h-1f9fffh ba70 4 kwords 1f8000h-1f8fffh ba69 32 kwords 1f0000h-1f7fffh ba68 32 kwords 1e8000h-1effffh ba67 32 kwords 1e0000h-1e7fffh ba66 32 kwords 1d8000h-1dffffh ba65 32 kwords 1d0000h-1d7fffh ba64 32 kwords 1c8000h-1cffffh ba63 32 kwords 1c0000h-1c7fffh bank 2 ba62 32 kwords 1b8000h-1bffffh ba61 32 kwords 1b0000h-1b7fffh ba60 32 kwords 1a8000h-1affffh ba59 32 kwords 1a0000h-1a7fffh ba58 32 kwords 198000h-19ffffh ba57 32 kwords 190000h-197fffh ba56 32 kwords 188000h-18ffffh ba55 32 kwords 180000h-187fffh ba54 32 kwords 178000h-17ffffh ba53 32 kwords 10000h-177fffh ba52 32 kwords 168000h-16ffffh ba51 32 kwords 160000h-167fffh ba50 32 kwords 158000h-15ffffh ba49 32 kwords 150000h-157fffh ba48 32 kwords 148000h-14ffffh ba47 32 kwords 140000h-147fffh ba46 32 kwords 138000h-13ffffh ba45 32 kwords 130000h-137fffh ba44 32 kwords 128000h-12ffffh ba43 32 kwords 120000h-127fffh ba42 32 kwords 118000h-11ffffh ba41 32 kwords 110000h-117fffh ba40 32 kwords 108000h-10ffffh ba39 32 kwords 100000h-107fffh
flash memory k8p3215uqb revision 1.1 april 2007 50 table 13. block architecture ( k8p3215uqb ) bank block block size (x16) address range bank 1 ba38 32 kwords 0f8000h-0fffffh ba37 32 kwords 0f0000h-0f7fffh ba36 32 kwords 0e8000h-0effffh ba35 32 kwords 0e0000h-0e7fffh ba34 32 kwords 0d8000h-0dffffh ba33 32 kwords 0d0000h-0d7fffh ba32 32 kwords 0c8000h-0cffffh ba31 32 kwords 0c0000h-0c7fffh ba30 32 kwords 0b8000h-0bffffh ba29 32 kwords 0b0000h-0b7fffh ba28 32 kwords 0a8000h-0affffh ba27 32 kwords 0a0000h-0a7fffh ba26 32 kwords 098000h-09ffffh ba25 32 kwords 090000h-097fffh ba24 32 kwords 088000h-08ffffh ba23 32 kwords 080000h-087fffh ba22 32 kwords 078000h-07ffffh ba21 32 kwords 070000h-077fffh ba20 32 kwords 068000h-06ffffh ba19 32 kwords 060000h-067fffh ba18 32 kwords 058000h-05ffffh ba17 32 kwords 050000h-057fffh ba16 32 kwords 048000h-04ffffh ba15 32 kwords 040000h-047fffh bank0 ba14 32 kwords 038000h-03ffffh ba13 32 kwords 030000h-037fffh ba12 32 kwords 028000h-02ffffh ba11 32 kwords 020000h-027fffh ba10 32 kwords 018000h-01ffffh ba9 32 kwords 010000h-017fffh ba8 32 kwords 008000h-00ffffh ba7 4 kwords 007000h-007fffh ba6 4 kwords 006000h-006fffh ba5 4 kwords 005000h-005fffh ba4 4 kwords 004000h-004fffh ba3 4 kwords 003000h-003fffh ba2 4 kwords 002000h-002fffh ba1 4 kwords 001000h-001fffh ba0 4 kwords 000000h-000fffh
flash memory k8p3215uqb revision 1.1 april 2007 51 package dimensions 64-ball fine ball grid array package (measured in millimeters) side view 0.10 max 0.50 1.20 13.00 to p vi e w bottom view a b c e g d f h 1.00 x 7=7.00 a 1.00x7= 7.00 3.50 64- ? 0.60solder ball 3.50 1.00 0.2 m a b ? (datum a) (datum b) 1.00 13.00 11.00 b 1 4 2 6 5 3 13.00 11.00 0.50 0.50 7 8 #a1 0.10 0.10 0.10 0.10 0.05 0.10 #a1 index mark (post reflow ? 0.62 0.05 )
flash memory k8p3215uqb revision 1.1 april 2007 52 package dimensions 48-ball fine ball grid array package (measured in millimeters) side view 0.45 0.05 0.10max 0.32 0.05 0.90 0.10 8.00 0.10 to p vi e w bottom view #a1 a b c e g d f h 0.80 x 5=4.00 a 0.80x7=5.60 2.00 48- ? 0.45 0.05 2.80 0.80 0.20 m a b ? (datum a) (datum b) 0.80 8.00 0.10 6.00 0.10 b 1 42 65 3 8.00 0.10 6.00 0.10 0.40 0.40 note 48fbga 6x8 package has same ball configuration with 48fbga 6x9 package of dual die package.
flash memory k8p3215uqb revision 1.1 april 2007 53 package dimensions 48-pin lead plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0.20 +0.07 -0.03 0.008 +0.003 -0.001 0.50 0.0197 #48 #25 0.488 12.40 max 12.00 0.472 0.10 0.004 max 0.25 0.010 () 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8?c 0.010 0.25 typ 0.125 +0.075 -0.035 0.005 +0.003 -0.001 0.50 0.020 ()

▲Up To Search▲

Price & Availability of K8P3215UQB-PE4B0

	To Download K8P3215UQB-PE4B0 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .